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PD - 96212
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits
G
IRFB3307ZGPBF
HEXFET(R) Power MOSFET
D
Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free l Halogen-Free
S
VDSS RDS(on) typ. max. ID (Silicon Limited) ID (Package Limited)
D
75V 4.6m: 5.8m: 120Ac 120A
G
D
S
TO-220AB IRFB3307ZGPBF
G
D
S
Gate
Drain
Max.
120 84 120 480 230 1.5 20 6.7 -55 to + 175 300 10lbfxin (1.1Nxm) 140 See Fig. 14, 15, 22a, 22b
Source
Units
A
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C ID @ TC = 25C IDM PD @TC = 25C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Wire Bond Limited) Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
d
W W/C V V/ns
f
C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche CurrentAd Repetitive Avalanche Energy
e
d
mJ A mJ
Thermal Resistance
Symbol
RJC RCS RJA Junction-to-Case Case-to-Sink, Flat Greased Surface , TO-220 Junction-to-Ambient, TO-220
j
Parameter
Typ.
--- 0.50 ---
Max.
0.65 --- 62
Units
C/W
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1
01/06/09
IRFB3307ZGPBF
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) RG(int) IDSS IGSS
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Internal Gate Resistance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage
Min. Typ. Max. Units
75 --- --- 2.0
---
Conditions
--- 0.094 4.6 --- 0.70 --- --- --- ---
--- --- 5.8 4.0 --- 20 250 100 -100
V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 5mAd m VGS = 10V, ID = 75A V VDS = VGS, ID = 150A
g
--- --- --- ---
A nA
VDS = 75V, VGS = 0V VDS = 75V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
--- 79 19 24 55 15 64 38 65 4750 420 190 440 410 --- 110 --- --- --- --- --- --- --- --- --- --- --- --- S nC
Conditions
VDS = 50V, ID = 75A ID = 75A VDS = 38V VGS = 10V ID = 75A, VDS =0V, VGS = 10V VDD = 49V ID = 75A RG = 2.6 VGS = 10V VGS = 0V VDS = 50V = 1.0MHz VGS = 0V, VDS = 0V to 60V VGS = 0V, VDS = 0V to 60V
320 --- --- --- --- --- --- --- --- --- --- --- Effective Output Capacitance (Energy Related)i --- --- Effective Output Capacitance (Time Related)h
g
ns
g
pF
i h
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)Adi Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- 120 --- 480 A
Conditions
MOSFET symbol showing the integral reverse
G D
S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 75A, VGS = 0V VR = 64V, --- 33 50 ns TJ = 25C TJ = 125C IF = 75A --- 39 59 di/dt = 100A/s --- 42 63 nC TJ = 25C TJ = 125C --- 56 84 --- 2.2 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
g
g
Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 120A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.050mH RG = 25, IAS = 75A, VGS =10V. Part not recommended for use above this value.
ISD 75A, di/dt 1570A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff. (ER) is a fixed capacitance that gives the same energy as R is measured at TJ approximately 90C.
Coss while VDS is rising from 0 to 80% VDSS.
2
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IRFB3307ZGPBF
1000
TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
1000
TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
100
BOTTOM
4.5V
4.5V 10
10
60s PULSE WIDTH
Tj = 25C 1 0.1 1 10 100 V DS, Drain-to-Source Voltage (V) 1 0.1 1
60s PULSE WIDTH
Tj = 175C 10
100
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
RDS(on) , Drain-to-Source On Resistance (Normalized)
Fig 2. Typical Output Characteristics
2.5 ID = 72A 2.0 VGS = 10V
ID, Drain-to-Source Current (A)
100 T J = 175C 10 T J = 25C
1.5
1 VDS = 25V 60s PULSE WIDTH 0.1 2 3 4 5 6 7 8
1.0
0.5 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (C)
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
100000
VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd
Fig 4. Normalized On-Resistance vs. Temperature
12.0 ID= 72A
VGS, Gate-to-Source Voltage (V)
10.0 8.0 6.0 4.0 2.0 0.0
C, Capacitance (pF)
VDS= 60V VDS= 38V VDS= 15V
10000 Ciss
1000
Coss Crss
100 1 10 VDS, Drain-to-Source Voltage (V) 100
0
10
20
30
40
50
60
70
80
90
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB3307ZGPBF
1000
10000 OPERATION IN THIS AREA LIMITED BY R DS(on)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
T J = 175C
1000
100
100sec
10
T J = 25C
1msec
10
10msec
1 VGS = 0V 0.1 0.0 0.5 1.0 1.5 2.0 VSD, Source-to-Drain Voltage (V)
DC
1
Tc = 25C Tj = 175C Single Pulse 1 10 VDS, Drain-to-Source Voltage (V) 100
0.1
Fig 7. Typical Source-Drain Diode Forward Voltage
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
120 100
ID, Drain Current (A)
Fig 8. Maximum Safe Operating Area
100 Id = 5mA 95 90 85 80 75 70 65 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( C )
80 60 40 20 0 25 50 75 100 125 150 175 T C , Case Temperature (C)
Fig 9. Maximum Drain Current vs. Case Temperature
1.2
Fig 10. Drain-to-Source Breakdown Voltage
600
EAS , Single Pulse Avalanche Energy (mJ)
1.0 0.8
500 400 300 200 100 0
ID 15A 26A BOTTOM 75A TOP
Energy (J)
0.6 0.4 0.2 0.0 20 30 40 50 60 70 80
25
50
75
100
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting T J , Junction Temperature (C)
4
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFB3307ZGPBF
1 D = 0.50 0.1 0.20 0.10 0.05 0.02 0.01
J J 1 R1 R1 2 R2 R2 R3 R3 3 C 3
Thermal Response ( Z thJC )
0.01
1
2
Ri (C/W) i (sec) 0.1164 0.000088 0.3009 0.001312 0.2313 0.009191
Ci= i/Ri Ci i/Ri
SINGLE PULSE ( THERMAL RESPONSE ) 0.001 1E-006
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 0.001 0.01 0.1
1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100 0.01
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse)
Avalanche Current (A)
0.05 10 0.10
1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 0.1 1.0E-06 1.0E-05 1.0E-04 tav (sec) 1.0E-03 1.0E-02 1.0E-01
Fig 14. Typical Avalanche Current vs.Pulsewidth
150 125 100 75 50 25 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C) TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 75A
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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EAR , Avalanche Energy (mJ)
5
IRFB3307ZGPBF
4.5
VGS(th), Gate threshold Voltage (V)
20 IF = 48A V R = 64V 15 TJ = 25C TJ = 125C
4.0 3.5 3.0
IRR (A)
2.5 2.0 1.5 1.0 0.5 -75 -50 -25 0 25 50 75 100 125 150 175 200 T J , Temperature ( C ) ID = 150A ID = 250A ID = 1.0mA ID = 1.0A
10
5
0 0 200 400 600 800 1000 diF /dt (A/s)
Fig 16. Threshold Voltage vs. Temperature
20 IF = 72A V R = 64V 15 TJ = 25C TJ = 125C
QRR (A)
Fig. 17 - Typical Recovery Current vs. dif/dt
420 IF = 48A V R = 64V TJ = 25C TJ = 125C
340
IRR (A)
260
10
180
5
100
0 0 200 400 600 800 1000 diF /dt (A/s)
20 0 200 400 600 800 1000 diF /dt (A/s)
Fig. 18 - Typical Recovery Current vs. dif/dt
420 IF = 72A V R = 64V TJ = 25C TJ = 125C
Fig. 19 - Typical Stored Charge vs. dif/dt
340
QRR (A)
260
180
100
20 0 200 400 600 800 1000 diF /dt (A/s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFB3307ZGPBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 21a. Unclamped Inductive Test Circuit
LD VDS
Fig 21b. Unclamped Inductive Waveforms
+
VDD D.U.T VGS Pulse Width < 1s Duty Factor < 0.1%
90%
VDS
10%
VGS
td(on) tr td(off) tf
Fig 22a. Switching Time Test Circuit
Fig 22b. Switching Time Waveforms
Id Vds Vgs
L
0
DUT 1K
VCC
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
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Fig 23a. Gate Charge Test Circuit
Fig 23b. Gate Charge Waveform
7
IRFB3307ZGPBF
Dimensions are shown in millimeters (inches)
TO-220AB Package Outline
TO-220AB Part Marking Information
@Y6HQG@) UCDTADTA6IADSA7#" BQ7A Ir)AABAAssvAvAhAirA vqvphrAAChytrAAArrA Ir)AAQAAvAhriyAyvrAvv vqvphrAAGrhqAAArrA DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G GPUA8P9@ Q6SUAIVH7@S 96U@A8P9@) 2G6TUA9DBDUAPA 86G@I96SA@6S XX2XPSFAX@@F Y2A68UPSA8P9@
TO-220AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
8
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.01/2009
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